In such a telecommunication system, bit groupings such as 8-bit bytes or octets from several lower-order frames are interleaved at a transmitting terminal in higher-order frame for subsequent redistribution to respective channels at a remote receiving terminal. Thus, the bit stream arriving at the latter terminal is organized in a succession of frames of m time slots each encompassing a group of n bits, with m=32 in many instances.
The recurrence rate of these n-bit groups in the arriving bit stream is determined by a clock at the transmitting end whose cadence may be reconstituted at the receiving terminal by a sync extractor operating as a so-called line clock. The rerouting of the interleaved bit groups at the demultiplexer output, however, must be controlled by clock pulses from a local source (also referred to as a "machine clock") whose frequency generally differs, however slightly, from that of the line clock. This is particularly the case with international communications where there is no central clock available for controlling the operations of equipment linked with both terminals. Differences in timing will also arise from the suppression of certain supervisory bits which travel with the message bits over the PCM signal path but which are no longer required on the channels to which the incoming bit groups are distributed, e.g. as described in commonly owned U.S. Pat. No. 4,147,895. That prior patent also discloses an expandable memory, serving as an elastic bit store, which is loaded under the control of clock pulses extracted from the incoming bit stream and is unloaded under the control of locally generated clock pulses of slightly different cadence.
The use of such an elastic bit store is designed to minimize the loss of information due to the disparity of the two clock-pulse cadences. Moreover, the lack of synchronism between the two clocks requires the provision of means for preventing the simultaneous appearance of loading and unloading commands which would impair the operation of the bit store. In the aforementioned prior patent this problem is solved by the use of an adjustable oscillator as the source of local clock pulses, the frequency of that oscillator being continuously adjusted by a phase comparator with inputs connected to a pair of counters respectively controlling the loading and the unloading of an n-stage buffer register. That solution, however, is inapplicable to a demultiplexer whose output side receives clock pulses from a source of fixed frequency, as where that source must also control operations in other parts of the system.